Search - DDS Verilog

[SCM] DDS

Description: 基于ｆｐｇａ，采用ｑｕａｒｔｕｓ２的ＤＤＳ信号发生器，采用高速ＤＡＣ９０８为数模芯片，并可通过５１单片机送入调制信号进行ＦＭ调制-Based on the fpga, the use of the DDS signal generator quartus2 using DAC908 number of high-speed chip module, and passed into 51 single-chip FM modulation signal modulation
Platform: | Size: 2745344 | Author: 张新 | Hits:

[VHDL-FPGA-Verilog] DDS1

Description: DDS信号发生器，能产生多种波形，正玄波，三角波，方波，频率可调，相位可调-DDS signal generator, can produce a variety of waveforms, are mysterious wave, triangle wave, square wave, frequency tunable, phase adjustable
Platform: | Size: 1108992 | Author: 张俊 | Hits:

[VHDL-FPGA-Verilog] oneperiod

Description: 将正弦波分割，数字化处理，即dds技术，为verilog做准备-Will be sinusoidal segmentation, digital processing, that is, dds technology, ready to do for the Verilog
Platform: | Size: 3072 | Author: 严新文 | Hits:

[VHDL-FPGA-Verilog] DDSverilogsource

Description: DDS的VERILOG原代码，请大家多支持-DDS of the Verilog source code, please support the U.S. more than
Platform: | Size: 3072 | Author: 屈开 | Hits:

[SCM] dds_quicklogic

Description: dds直接频率合成源代码，基于rom表方式-dds a direct frequency synthesizer source code, based on the way rom Table
Platform: | Size: 22528 | Author: zhangxi | Hits:

[VHDL-FPGA-Verilog] dds_using_FPGA

Description: verilog编写基于fpga的DDS实现-Verilog prepared based on the FPGA to achieve the DDS
Platform: | Size: 448512 | Author: 宇天 | Hits:

[Other] code_for_wireless_communication

Description: 包含软件无线电、dds、滤波器设计、数字调制解调等常用无线通信设计的matlab\verilog源码-Contains software radio, dds, filter design, digital modulation and demodulation of wireless communication, such as commonly used design matlabverilog source
Platform: | Size: 197632 | Author: 李大鹏 | Hits:

[SCM] DDS

Description: 直接频率合成仿真源程序,希望有人能用到.-Direct frequency synthesizer simulation source code, hope someone can use to.
Platform: | Size: 10240 | Author: bajunsheng | Hits:

[Other] DDS

Description: 基于DDS技术的函数波形发生器设计，适合用fpga设计波形发生器用-Based on DDS technology function waveform generator design, suitable for FPGA design with Waveform Generator
Platform: | Size: 1682432 | Author: | Hits:

[VHDL-FPGA-Verilog] AM

Description: FPGA内AM调制工程。内带调制波、载波生成。关键词：FPGA verilog AM DDS-AM modulation works within the FPGA. Within the band modulation wave generated carrier. Key words: FPGA verilog AM DDS
Platform: | Size: 1687552 | Author: baixiangzhou | Hits:

[VHDL-FPGA-Verilog] high_speed_tap8_DDS

Description: 用verilog编写的高速8路并行dds模块，用于与高速da(1ghz或以上)接口产生任意频率正弦波，模块已经经过工程验证，用于产品中。-Verilog prepared with high-speed 8-way parallel dds modules for use with high-speed da (1ghz or above) interface have any frequency sine wave, the module has been proof for the products.
Platform: | Size: 5120 | Author: yangyu | Hits:

[SCM] dds

Description: 关于FPGA中DDS核参数设置的资料，英文版的XILINX资料-DDS on the FPGA in the data set of nuclear parameters, the English version of XILINX information
Platform: | Size: 1664000 | Author: 李晶 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: Quartus中实现的DDS 使用的是altera提供的IP core-DDS achieved Quartus using IP core provided by altera
Platform: | Size: 83968 | Author: ray | Hits:

[source in ebook] AD9910Driver

Description: DDS之AD9910驱动源码，控制器ARM ADuc7026.-DDS source of the AD9910 driver, controller ARM ADuc7026.
Platform: | Size: 139264 | Author: 彭梁栋 | Hits:

[VHDL-FPGA-Verilog] DDS-top

Description: 能够基于DDS实现输出正弦波形的一部分程序，利用Verilog HDL语言编写。-Able to achieve based on the DDS output sine wave-shaped part of the procedure, the use of Verilog HDL language.
Platform: | Size: 299008 | Author: evil | Hits:

[Graph Drawing] dds(heli)

Description: DDS用verilog 实现，可以实现方波、正弦和三角-DDS using verilog realized, can be square wave, sinusoidal and triangular
Platform: | Size: 428032 | Author: qian | Hits:

[VHDL-FPGA-Verilog] dds

Description: 基于FPGA的DDS设计，本程序采用verilog HDL语言编写，使用DDS+Pll倍频-The DDS-based FPGA design, the procedures used verilog HDL language, the use of DDS+ Pll frequency
Platform: | Size: 190464 | Author: 赵一 | Hits:

[VHDL-FPGA-Verilog] dds_easy

Description: 直接频率合成DDS模块的ise工程，可以直接下载，在Spartan3/Spartan3E上验证通过。该DDS模块可以产生双通道的不同频率的正弦波，也可以产生同频的任意相位差的相移波形。本模块累加器位数为32位，可以产生12位相位精度12位量化精度的正弦波。该设计例化一个Block Ram，为节省储存空间仅需要储存1/4周期的数据。根据需要，可以重新修改数据，改变波形。-DDS direct frequency synthesizer module ，ise project, can be directly downloaded through the Spartan3/Spartan3E and tested successfully. The DDS module can generate two-channel sine wave of different frequency, or produce the same frequency arbitrary waveform phase difference of the phase shift. There is a 32-bit accumulator to generate 12 bit phase-precision 12-bit quantization precision of the sine wave. Cases the design of a Block Ram, in order to save storage space need to store only 1/4 cycle of data. Necessary, can modify data, change the waveform.
Platform: | Size: 471040 | Author: 郭先生 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 用VERILOG语言实现的dds(直接数字频率合成器)-VERILOG language with the dds (DDS)
Platform: | Size: 104448 | Author: 叶少朋 | Hits:

[VHDL-FPGA-Verilog] cordicDDS

Description: Cordic算法实现DDS的Verilog 源码,14位精度，非常实用的。-DDS algorithm Cordic the Verilog source code, 14-bit accuracy, very practical.
Platform: | Size: 7168 | Author: 王王 | Hits:

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[SCM] DDS

[VHDL-FPGA-Verilog] DDS1

[VHDL-FPGA-Verilog] oneperiod

[VHDL-FPGA-Verilog] DDSverilogsource

[SCM] dds_quicklogic

[VHDL-FPGA-Verilog] dds_using_FPGA

[Other] code_for_wireless_communication

[SCM] DDS

[Other] DDS

[VHDL-FPGA-Verilog] AM

[VHDL-FPGA-Verilog] high_speed_tap8_DDS

[SCM] dds

[VHDL-FPGA-Verilog] DDS

[source in ebook] AD9910Driver

[VHDL-FPGA-Verilog] DDS-top

[Graph Drawing] dds(heli)

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] dds_easy

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] cordicDDS

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